P. Hénon,
F. Pellegrini,
P. Ramet,
and J. Roman.
Blocking Issues for an Efficient Parallel Block ILU Preconditioner.
In International SIAM Conference On Preconditioning Techniques For Large Sparse Matrix Problems In Scientific And Industrial Applications,
Atlanta, USA,
May 2005.
Keyword(s): Sparse.
@InProceedings{C:LaBRI::pre05,
author = {H\'enon, P. and Pellegrini, F. and Ramet, P. and Roman, J.},
title = {Blocking Issues for an Efficient Parallel Block ILU Preconditioner},
booktitle = {International SIAM Conference On Preconditioning Techniques For Large Sparse Matrix Problems In Scientific And Industrial Applications},
OPTcrossref = {},
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OPTpages = {},
year = {2005},
OPTeditor = {},
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OPTseries = {},
address = {Atlanta, USA},
month = may,
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URL = {http://www.labri.fr/~ramet/restricted/pred2005.ps},
KEYWORDS = "Sparse"
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P. Hénon,
P. Ramet,
and J. Roman.
On using an hybrid MPI-Thread programming for the implementation of a parallel sparse direct solver on a network of SMP nodes.
In Proceedings of Sixth International Conference on Parallel Processing and Applied Mathematics, Workshop HPC Linear Algebra,
volume 3911 of LNCS,
Poznan, Poland,
pages 1050-1057,
September 2005.
Springer Verlag.
Keyword(s): Sparse.
Abstract:
Since the last decade, most of the supercomputer architectures are based on cluster of SMP nodes. In those architectures the exchanges between processors are made through shared memory when the processor are located on a same SMP node and through the network otherwise. Generally, the MPI implementations provided by the constructor on those machines are adapted to this situation and take advantage of the share memory to treat messages between processors in a same SMP node. Nevertheless, this transparent approach to exploit shared memory do not avoid the storage of buffers needed in asynchronous communications. In the parallel direct solvers the storage of these buffers can become a bottleneck. In this paper, we propose an hybrid thread-MPI implementation of a direct solver and analyse the benefits of this approach in term of memory and run-time performances. |
@InProceedings{C:LaBRI::ppam05,
author = "H\'enon, P. and Ramet, P. and Roman, J.",
title = "On using an hybrid MPI-Thread programming for the implementation of a parallel sparse direct solver on a network of SMP nodes",
booktitle = "Proceedings of Sixth International Conference on Parallel Processing and Applied Mathematics, Workshop HPC Linear Algebra",
OPTcrossref = {},
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OPTeditor = {},
volume = {3911},
OPTnumber = {},
series = {LNCS},
year = "2005",
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publisher = {Springer Verlag},
address = {Poznan, Poland},
month = sep,
pages = {1050--1057},
OPTnote = {},
OPTannote = {},
URL = {http://www.labri.fr/~ramet/restricted/ppam05.ps},
KEYWORDS = "Sparse",
ABSTRACT = { Since the last decade, most of the supercomputer architectures are based on cluster of SMP nodes. In those architectures the exchanges between processors are made through shared memory when the processor are located on a same SMP node and through the network otherwise. Generally, the MPI implementations provided by the constructor on those machines are adapted to this situation and take advantage of the share memory to treat messages between processors in a same SMP node. Nevertheless, this transparent approach to exploit shared memory do not avoid the storage of buffers needed in asynchronous communications. In the parallel direct solvers the storage of these buffers can become a bottleneck. In this paper, we propose an hybrid thread-MPI implementation of a direct solver and analyse the benefits of this approach in term of memory and run-time performances. }
}